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MR2A16A
Table 10 – Write Cycle Timing 2 ( E Controlled)
Parameter 1
Write cycle time 2
Address set-up time
Address valid to end of write ( G high)
Address valid to end of write ( G low)
Enable to end of write ( G high)
Enable to end of write ( G low) 3
Data valid to end of write
Data hold time
Write recovery time
Symbol
t AVAV
t AVEL
t AVEH
t AVEH
t ELEH
t ELWH
t ELEH
t ELWH
t DVEH
t EHDX
t EHAX
Min
35
0
18
20
15
15
10
0
12
Max
-
-
-
-
-
-
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus
contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after
W goes low, the output will remain in a high impedance state. After W, E or UB /LB has been brought high, the signal must
remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being
asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device.
2. All write cycle timings are referenced from the last valid address to the first transition address.
3. If E goes low at the same time or after W goes low, the output will remain in a high-impedance state. If E goes high at the
same time or before W goes high, the output will remain in a high-impedance state.
Figure 9 – Write Cycle Timing 2 ( E Controlled)
t AVAV
A (ADDRESS)
E (CHIP ENABLE)
W (WRITE ENABLE)
UB, LB (BYTE ENABLE)
t AVEL
t AVEH
t ELEH
t ELWH
t EHAX
t DVEH
t EHDX
D (DATA IN)
Q (DATA OUT)
Hi-Z
Data Valid
Copyright ? Everspin Technologies 2013
13
MR2A16A Rev. 11, 10/2013
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